A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address

Q. A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

(A) 24 bits and 0 bits

(B) 28 bits and 4 bits

(C) 24 bits and 4 bits

(D) 28 bits and 0 bits

Ans: 28 bits and 0 bits

Solution:

Given cache block size is 16 bytes, so block or word offset is 4 bits. Fully associative cache of size 16 kB, so line offset should be,

= cache size / block size

= 16 kB / 16 B

= 1 k

= 1024

= 10 bits Line or Index Offset

Tag bit size would be,

= processor address size – (line offset + word offset)

= 32 – 10 – 4

= 18 bits tag size

Since, there no option matches, but if we assume that Line Offset is a part of Tag bits, therefore,

Tag bits = 18+10 = 28 bits

Line or Index offset = 0 bits (since fully associative cache memory),

Word or block offset = 4 bits