Q. In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data π·ππ using clock πΆπΎ. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of Ξπ/ππΆπΎ = 0.15, where the parameters Ξπ and ππΆπΎ are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.
If the probability of input data bit (π·ππ) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node π, is
Ans: 0.82 – 0.86
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