Q. A 2-bit synchronous counter using two J-K flip flops is shown. The expressions for the inputs to the J-K flip flops are also shown in the figure. The output sequence of the counter starting from Q1Q2 = 00 is
(A) 00 → 11 → 10 → 01 → 00 …
(B) 00 → 01 → 10 → 11 → 00 …
(C) 00 → 01 → 11 → 10 → 00 …
(D) 00 → 10 → 11 → 01 → 00 …
Ans: 00 → 01 → 11 → 10 → 00 …
![Determine the correctness (or otherwise) of the following Assertion [A] and the Reason [R]](https://www.gkseries.com/blog/wp-content/uploads/2023/10/Determine-the-correctness-or-otherwise-of-the-following-Assertion-A-and-the-Reason-R.jpg)
