A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock.
Q. A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is ____________× 106 bytes/sec.
Solution:
8 W ———- 12 cycles
8 × 4 bytes ——— 12 cycles
? B ———— 1 sec
= { (8*4 bytes) / (12 cycles) } * 60 MHz clock
= { (32 bytes) / (12 cycles) } * 60 * 106Hz cycles / second
= {(32 * 60) / (12)} bytes / second
= 160 bytes / second