Q. In the circuit shown below, assume that the comparators are ideal and all components have zero propagation delay. In one period of the input signal πππ = 6 sin(ππ‘), the fraction of the time for which the output OUT is in logic state HIGH is
Sol:
The output represents X-NOR gate.
So, the given diagram can be simplified as
0 β€ Vin < 3 happens for the period 0 to 30Β° and 150Β° to 180Β° the output is high for, 30 to 150Β° and 180Β° to 360Β° Total period gets high output = 300
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