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Q. An e-mail password must contain three characters. The password has to contain one numeral from 0 to 9, one upper case and one lower case character from the English alphabet. How many distinct passwords are possible? (A) 6,760(B) 13,520(C) 40,560(D) 1,05,456 Ans: 40,560

Q. The three roots of the equation 𝑓(𝑥) = 0 are 𝑥 = {−2, 0, 3}. What are the three values of 𝑥 for which 𝑓(𝑥 − 3) = 0? (A) −5, −3, 0(B) −2, 0, 3(C) 0, 6, 8(D) 1, 3, 6 Ans: 1, 3, 6

Q. “A common misconception among writers is that sentence structure mirrors thought; the more __________the structure, the more complicated the ideas.” The word that best fills the blank in the above sentence is (A) detailed(B) simple(C) clear(D) convoluted Ans: convoluted

Q. “Since you have gone off the__________, the___________sand is likely to damage the car.” The words that best fill the blanks in the above sentence are (A) course, ...

Q. A band limited low-pass signal 𝑥(𝑡) of bandwidth 5 kHz is sampled at a sampling rate 𝑓𝑠. The signal 𝑥(𝑡) is reconstructed using the reconstruction filter 𝐻(𝑓) whose magnitude response is shown below: The minimum sampling rate 𝑓𝑠 (in kHz) for perfect reconstruction of 𝑥(𝑡) ...

Q. Consider the network shown below with 𝑅1 = 1Ω, 𝑅2 = 2Ω and 𝑅3 = 3Ω. The network is connected to a constant voltage source of 11V. The magnitude of the current (in amperes, accurate to two decimal places) through the source is  Ans: 7.9 - 8.1

Q. The contour C given below is on the complex plane z = x + jy , where j =√ -1         The value of the integral is ______ Ans: 2

Q. A uniform plane wave traveling in free space and having the electric field is incident on a dielectric medium (relative permittivity > 1, relative permeability = 1) as shown in the figure and there is no reflected wave. The relative permittivity (correct to two decimal places) of ...

Q. The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to ...

Q. In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data 𝐷𝑖𝑛 using clock 𝐶𝐾. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of Δ𝑇/𝑇𝐶𝐾 = 0.15, where the parameters Δ𝑇 ...