gate questions
In the circuit shown, 𝑉𝑠 is a square wave of period 𝑇 with maximum and minimum values of 8 V and -10 V, respectively. Assume that the diode

Q. In the circuit shown, 𝑉𝑠 is a square wave of period 𝑇 with maximum and minimum values of 8 V and -10 V, respectively. Assume that the diode is ideal and 𝑅1 = 𝑅2 = 50 Ξ©. The average value of 𝑉𝐿 is______volts (rounded off to 1 decimal place). Ans: -3.1 - -2.9

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The baseband signal π‘š(𝑑) shown in the figure is phase-modulated to generate the PM signal πœ‘(𝑑) = cos(2πœ‹π‘“π‘π‘‘ + π‘˜ π‘š(𝑑)). The time 𝑑 on the x-axis in the figure is in milliseconds

Q. The baseband signal π‘š(𝑑) shown in the figure is phase-modulated to generate the PM signal πœ‘(𝑑) = cos(2πœ‹π‘“π‘π‘‘ + π‘˜ π‘š(𝑑)). The time 𝑑 on the x-axis in the figure is in milliseconds. If the carrier frequency is 𝑓𝑐 = 50 kHz and π‘˜ = 10πœ‹, then the ratio of the minimum instantaneous frequency (in kHz) to ...

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If 𝑋 and π‘Œ are random variables such that 𝐸[2𝑋 + π‘Œ] = 0 and 𝐸[𝑋 + 2π‘Œ] = 33, then 𝐸[𝑋] + 𝐸[π‘Œ] =Β 

Q. If 𝑋 and π‘Œ are random variables such that 𝐸 = 0 and 𝐸 = 33, then 𝐸 + 𝐸 =Β Β Β Β Β Β Β Β Β Β  . Ans:11 Solution: E = E + E E = A E Where E represents the expected or mean value of the random variable 'x' Application: E = 0 2E + E = 0Β  Β Β ----(1) E = 33 E + 2E = ...

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A standard CMOS inverter is designed with equal rise and fall times (β𝑛 = Ξ²p). If the width of the pMOS transistor in the inverter is increased

Q. A standard CMOS inverter is designed with equal rise and fall times (β𝑛 = Ξ²p). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (𝑁𝑀𝐿) and the HIGH noise margin 𝑁𝑀𝐻? A. 𝑁𝑀𝐿 increases and 𝑁𝑀𝐻 decreases. B. 𝑁𝑀𝐿 decreases and ...

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