![The figure below shows the ๐๐กโ full-adder block of a binary adder circuit. Ci is the input carry and Ci+1 is the output carry of the circuit. Assume that](https://www.gkseries.com/blog/wp-content/uploads/2023/08/The-figure-below-shows-the-๐๐กโ-full-adder-block-of-a-binary-adder-circuit.-Ci-is-the-input-carry-and-Ci1-is-the-output-carry-of-the-circuit.-Assume-that.jpg)
Q. The figure below shows the ๐๐กโ full-adder block of a binary adder circuit. Ci is the input carry and Ci+1 is the output carry of the circuit. Assume that each logic gate has a delay of 2 nanosecond, with no additional time delay due to the interconnecting wires. If the inputs Ai , Bi are available and stable throughout the carry propagation, the maximum time taken for an input Ci to produce a steady-state output Ci+1 is _____nanosecond.
![](https://www.gkseries.com/blog/wp-content/uploads/2023/08/image-36.png)
Sol:
Given that Ai and Bi are available throughout the carry propagation. The maximum time taken for an input C1 to produce a steady state output Ci+1 involves two gates as shown in figure. Each gate has a delay of 2ns Total time delay = 4 ns.