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Free download in PDF Microcontrollers and Applications Multiple Choice Questions with Answers for competitive exams. These short objective type questions with answers are very important for Board exams as well as competitive exams. These short solved questions or quizzes are provided by Gkseries.
61
Which potential mode of operation indicate the frequent sending of byte to the slave corresponding to the reception of an acknowledge signal when it becomes desirable for the master to write to the slave during data transmission in I2C bus?
[A]
Master in master-transmit mode & Slave in slave-receive mode
[B]
Slave in slave-transmit mode & Master in master-receive mode
[C]
Master in master-transmit mode as well as master-receive mode
[D]
Slave in slave-transmit mode as well as slave-receive mode
Answer: Master in master-transmit mode & Slave in slave-receive mode
62
What is the directional nature of two active wires SDA & SCL usually adopted in I2C Bus for carrying the information between the devices?
[A]
Uni-directional
[B]
Bi-directional
[C]
Multi-directional
[D]
None of the above
63
What does an IC that initiate or enable the data transfer on bus can be regarded as, in accordance to the I2c protocol specifications?
[A]
Bus Master
[B]
Bus Slaves
[C]
Bus Drivers
[D]
Bus Data Carriers
64
Which mechanism automates the enabling of RS485 transceiver with an elimination of hardware handshake line during each time of the data transmission?
[A]
RTS Control
[B]
Send Data Control
[C]
Tri-State Control
[D]
Bit-wise Enable Timing Control
Answer: Send Data Control
65
Which protocol standard of serial communication specify the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration?
[A]
RS232
[B]
RS2485
[C]
RS422
[D]
RS423
66
Which among the below stated lines represent the handshaking variant usually and only controlled by the software in the handshaking process?
[A]
XON/ XOFF
[B]
DCD & GND
[C]
TxD & RxD
[D]
All of the above
67
Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232?
[A]
CD & IR
[B]
DSR & DTR
[C]
RTS & CTS
[D]
None of the above
68
Which characteristics of an embedded system exhibit the responsiveness to the assortments or variations in system’s environment by computing specific results for real-time applications without any kind of postponement?
[A]
Single-functioned Characteristics
[B]
Tightly-constraint Characteristics
[C]
Reactive & Real time Characteristics
[D]
All of the above
Answer: Reactive & Real time Characteristics
69
Which abstraction level undergo the compilation process by converting a sequential program into finite-state machine and register transfers while designing an embedded system?
[A]
System
[B]
Behaviour
[C]
RT
[D]
Logic
70
What are the essential tight constraint/s related to the design metrics of an embedded system?
[A]
Ability to fit on a single chip
[B]
Low power consumption
[C]
Fast data processing for real-time operations
[D]
All of the above
71
Which feature deals with the fetching of next instruction during the execution of current instruction irrespective of the memory access?
[A]
Fetching
[B]
Pre-fetching
[C]
Fetch & Decoding
[D]
All of the above
72
Which kind of multiplexing scheme is adopted by Von-Newman architecture especially for program and data fetching purposes?
[A]
Time Division Multiplexing
[B]
Frequency Division Multiplexing
[C]
Statistical Time Division Multiplexing
[D]
Code Division Multiplexing
Answer: Time Division Multiplexing
73
Which factors/parameters contribute to an effective utilization or adoption of Harvard architecture by most of the DSPs for streaming data?
[A]
Greater memory bandwidth
[B]
Predictable nature of bandwidth
[C]
Both a & b
[D]
None of the above
74
Which architectural scheme has a provision of two sets for address & data buses between CPU and memory?
[A]
Harvard architecture
[B]
Von-Neumann architecture
[C]
Princeton architecture
[D]
All of the above
Answer: Harvard architecture
75
Which register of current procedure resemble physically similar to the parameter register of called procedure during register to register operation in an overlapping window of RISC Processors?
[A]
Local Register
[B]
Temporary Register
[C]
Parameter Register
[D]
All of the above
Answer: Temporary Register
76
What does the compact and uniform nature of instructions in RISC processors facilitate to?
[A]
Compiler optimization
[B]
Pipelining
[C]
Large memory footprints
[D]
None of the above
77
What are the significant designing issues/factors taken into consideration for RISC Processors?
[A]
Simplicity in Instruction Set
[B]
Pipeline Instruction Optimization
[C]
Register Usage Optimization
[D]
All of the above
78
How are the address and data buses removed in external memory type of microcontrollers?
[A]
Through demultiplexing by external latch & ALE signal
[B]
Through demultiplexing by external latch & DLE signal
[C]
Through multiplexing by external latch & DLE signal
[D]
Through multiplexing by external latch & ALE signal
Answer: Through multiplexing by external latch & ALE signal
79
External Memory Microcontrollers can overcome the limitations of insufficient in-built program and data memory by allowing the connections of external memory using _________
[A]
Serial Port Pins as address and data lines
[B]
Parallel Port Pins as address and data lines
[C]
Parallel Port Pins as address and control lines
[D]
Serial Port Pins as address and control lines
Answer: Parallel Port Pins as address and data lines
80
Which microcontrollers offer the provisional and salient software features of fault handling capability, interrupt vector efficiency and versatile addressing?
[A]
TMS 1000 (4 bit)
[B]
TMS 7500 (8 bit)
[C]
Intel 8096 (16 bit)
[D]
Intel 80960 (32 bit)
Answer: Intel 80960 (32 bit)
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